Advanced complementary metal oxide semiconductor (CMOS) devices are increasingly utilizing metal gate electrodes in order to avoid the “poly-Si depletion” and “boron penetration” effects observed with traditional gate electrodes of doped polycrystalline silicon (poly-Si). The selection of a particular metal for a gate material is guided by a number of considerations, including the work function and electrical resistivity desired for the gate, the thermal budget that the gate metal will be expected to survive, the type of gate dielectric (high-k or conventional), and the existence of a damage-free gate metal deposition process. Though mid-gap metals such as tungsten might be usable for both n-type field effect transistors (n-FETs) and p-type FETs (p-FETs) in CMOS, it is desirable to use one (high work function) gate metal appropriate for p-FETs and another (low work function) gate metal appropriate for n-FETs, in a design approach known as “dual metal/dual work function” CMOS.
Such dual metal/dual work function schemes can be very complex if the two different metals require different deposition and patterning processes. This is especially true when the patterning is done subtractively, since the second metal to be deposited must be removed without damaging the first. The complexity of such dual metal/dual work function schemes for CMOS metal gates has thus led to increased interest in “single metal/dual work function” schemes in which a single gate material is deposited over n-FET and p-FET device areas and then modified so that it has an n-FET-appropriate work function in n-FET device areas and a p-FET-appropriate work function in p-FET device areas.
Approaches to “single metal/dual work function” have been described in the literature. One approach [V. Misra et al., IEEE Electron Device Letters 23 354 (2002) and H. Zhong et al., IEDM Tech. Dig. 467 (2001)], suggests depositing a Ru—Ta alloy layer with an n-FET work function over n-FET and p-FET device areas and then converting the Ru—Ta alloy into a Ru-rich Ru—Ta alloy with a p-FET work function (in the p-FET device areas) by depositing additional Ru and annealing.
In another approach, a metal such as Mo with a p-FET work function is deposited over n-FET and p-FET device areas and converted into a Mo nitride having a n-FET work function (in n-FET device regions) by either ion implantation of nitrogen [P. Ranade et al., Mat. Res. Soc. Proc. 670 K5.2 (2001); R. Lin et al., IEEE Electron Device Letters 23 49 (2002)] or solid state diffusion/reaction of nitrogen from an N-rich overlayer of TiN [R. J. P. Lander et al., Mat. Res. Soc. Symp. Proc. 716 B5.11 (2002)].
A drawback of the nitrogen ion implantation approach is that it can damage the underlying gate dielectric [T. Amada et al., Mat. Res. Soc. Symp. Proc. 716 B7.5 (2002)]. Solid state diffusion of nitrogen from TiN results in less damage, but does not quite provide sufficient change in the work function (˜−0.5 eV observed for Mo on SiO2, ˜−0.75 eV is desired). Drawbacks of the Ru-Ta alloy approach include the potential for tantalum reaction with the gate dielectric, and the lack of chemical vapor deposition (CVD) methods for the Ru-Ta alloy (since CVD is one of the few deposition processes that is free from dielectric-damaging charged particle bombardment).